The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having step gates to improve overall signal transfer rate, and a method of manufacturing the same.
In conventional dynamic random access memories (DRAMs), a gate stack is provided on a semiconductor substrate having a trench isolation film, and a source/drain junction region is provided on the semiconductor substrate at both sides of the gate stack. A gate having such a structure is called a planar gate. The planar gate has a short channel length between the source and drain, and therefore exhibits fast operating speed due to the low resistance of the channel.
However, the increased degree of integration of DRAM cells leads to a decrease in the size of the transistors, which in turn results in a shortened channel length between the source and drain. As a result, short-channel effects (SCF) of the transistors become severe, thus decreasing the threshold voltage. In order to prevent a decrease of threshold voltage due to short-channel effects of the transistors, the channel doping concentration has conventionally been increased in order to obtain desired magnitude of threshold voltage.
However, such increased channel doping concentration leads to localized electricfield enhancement effects in source junctions and increased leakage current, thereby aggravating the refresh properties of DRAM memory cells. Therefore, recess channel structures, which are capable of inhibiting the above-mentioned issues without decreasing the degree of integration of the device via the lengthening of the effective channel by etching a portion of a substrate to a given depth, are being actively researched. Among such recess channel structures, step gate stack structures, in which the lower part of the gate is formed into a step shape, thereby being capable of lengthening the channel, are receiving a great deal of attention in the art.
FIG. 1 is a cross-sectional view showing a step gate structure of a semiconductor device having a recess channel in accordance with a conventional art.
As shown in FIG. 1, trench isolation films 110 defining an active region are provided in a semiconductor substrate 100. The trench isolation films 110 are made of insulating films, for example oxide films. Step gate stacks 120 are provided on the semiconductor substrate 100, and the step gate stacks 120 take step-like profiles having upper/lower and vertical surfaces on lower parts thereof. Source regions such as first impurity regions 130 and a drain region as a second impurity region 135 are provided on the semiconductor substrate 100 at both sides of the step gate stacks 120. A gate insulating film 101 is deposited at the lower part of the step gate stacks 120. In addition, even though they are not shown in FIG. 1, bottom electrode films, which are electrically connected to the first impurity regions 130 provided in the semiconductor substrate 100, capacitors (not shown) including a dielectric film and top electrode film sequentially formed on the bottom electrode films, and a bit line stack (not shown) connected to the second impurity region 135 are formed on the substrate.
As described above, since the step gate of the semiconductor device has a long channel length due to the step-like profiles having upper/lower and vertical surfaces, it is possible to prevent the localized electric-field enhancement effects in source junctions without increasing the channel doping concentration, thus decreasing leakage current. However, prolonged channel length results in increased resistance of the device which in turn decreases the signal transfer rate of the overall DRAM.